1. Technical Field
Various embodiments relate to a semiconductor device, and more particularly, to a nonvolatile memory device that includes a resistive memory cell, and to a semiconductor system using the same.
2. Related Art
Dynamic random access memory (DRAM) stores data by charging and discharging a memory cell comprising a capacitor. DRAM is volatile memory because leakage current flows out of the capacitor. Various research has been conducted with the goal of realizing a memory device that is nonvolatile and thus obviates the need for separate data storage. Particularly, there are ongoing efforts to realize non-volatility by changing the material of the memory cell, one ongoing effort of which is to realize a memory device that includes a resistive memory cell.
The resistive memory device includes a memory cell made of variable resistive material, where the memory cells variable resistance depends on the amount of current running through the material. Thus we can store data in the memory cell by changing the amount of current flowing into a resistive memory cell. For example, a memory cell exhibiting high resistance may have data ‘0’ and a memory cell exhibiting low resistance may have data ‘1’.
FIG. 1 is a graph illustrating a resistance distribution of a multi-level cell.
The variable resistive material may have 3 or more states of resistance, which makes the memory cell capable of storing multi-level data. As illustrated in FIG. 1, a multi-level cell may have 4 resistance distributions and store 2 bits of data, each of whose values has a corresponding unique logic value based on the resistance distributions.
For example, data distributed in a range over a resistance value of R/2 may represent the logic value ‘11’. Data distributed in a range between resistance values of R/2 and R/3 may represent the logic value ‘10’. Data distributed in a range between resistance values of R/3 and R/4 may represent the logic value ‘01’. Data distributed in a range under a resistance value of R/4 may represent the logic value ‘00’.
It is important that a resistive memory device having a multi-level cell accurately read and write data based on the resistance distributions. In the case of 4 resistance distributions, as illustrated in FIG. 1, 3 or more reference currents or voltages are needed to accurately detect data stored in the memory cell. A resistive memory device may include a reference cell for generating the reference current or voltage. The resistive memory device keeps changing the resistive status of the reference cell and generates the reference current or voltage in order to read the data stored in the memory cell.